Method for forming self-aligned local-halo metal-oxide-semiconductor device

ABSTRACT

A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method for forming a raisedsource/drain semiconductor device, and more particularly to a method forforming a local-halo semiconductor device with raised source/drain.

[0003] 2. Description of the Prior Art

[0004] As semiconductor devices are scaled to smaller dimensions,generally in the sub-0.1 μm region, it is highly desirable and generallynecessary to fabricate such devices with source/drain shallow junctionand a controllable halo implant region adjacent to the source/drainshallow junction to reduce short channel effects, such as subsurfacepunchthrough and hot carrier effect. The halo implant region is a dopedimplanted region, which is oppositely doped to the shallow junctionregion. However, when a silicide is formed on the source/drain region,the silicide easily contacts with the shallow junction to make junctionleakage. Therefore, an approach to resolve the leakage problem is to useraised source/drain. Since the raised source/drain is formed upwardabove the substrate, the silicide could not easily contact with theshallow junction, and then the junction leakage can be reduced.

[0005]FIG. 1A to 1C shows various steps for forming a conventionalN-channel metal-oxide-semiconductor (MOS) device with raisedsource/drain. The conventional method comprises the following steps.Firstly, referring to FIG. 1A, a P type semiconductor substrate 100 isprovided. A plurality of shallow trench isolation 101 is formed in thesubstrate 100. Then, a gate oxide 102 and a gate electrode 103 aresequentially formed between each pair of the shallow trench isolation101 on the substrate 100. Subsequently, placing an implant mask on thesubstrate 100 and by way of ion implantation, to form an N type lightlydoped drain region 104 between the gate electrode 103 and each of thepair of shallow trench isolation 101 in the substrate 100. And then,performing halo implantation to form a halo implant region 105 with Ptype conductivity surrounding each of the lightly doped drain region104.

[0006] Secondly, referring to FIG. 1B, forming a conformal silicondioxide layer 106 on the gate electrode 103 and then forming a siliconnitride layer 107 on the conformal silicon dioxide layer 106. Theconformal silicon dioxide layer 106 is anisotropically etched by way ofreactive ion etch method to form a pair of first sidewall spacers 106 onopposite sides of the gate electrode 103 and a pair of second sidewallspacers 107 on the opposite sides of the first sidewall spacer 106.

[0007] Finally, referring to FIG. 1C, forming a raised source/drain 108upward on each of the pair of the lightly doped drain region 104.However, there are some disadvantages existing in this conventionalmethod. One is the halo implant region 105 surrounding the lightly dopeddrain region 104 increases the junction capacitance, resulting in aslower operation speed for the MOS device. The other is the misalignmentof the ion implant mask can cause changeable LDD/halo implant regions.

[0008] Accordingly, it is desirable to provide a method for forming alocal halo MOS device with raised source/drain to reduce the junctioncapacitance and also overcome the drawbacks of the conventional method.

SUMMARY OF THE INVENTION

[0009] It is an objective of the present invention to provide a methodfor forming a self-aligned local-halo metal-oxide-semiconductor (MOS)device with raised source/drain, in which a gate electrode and theraised source/drain act as the self-aligned masks, a LDD/haloimplantation is performed to form a local LDD/halo diffusion regiontherebetween in the substrate. The local LDD/halo diffusion regionreduces the junction capacitance. Thereby, the operation speed of theMOS device is facilitated.

[0010] Another objective of the present invention is to provide a methodfor forming a self-aligned local-halo metal-oxide-semiconductor (MOS)device with raised source/drain, in which a gate electrode and theraised source/drain act as self-aligned masks to form a local LDD/halodiffusion region therebetween. Therefore, an extra mask is not necessaryand then the manufacturing process is simplified.

[0011] In order to achieve the above objectives, the present inventionprovides a method for forming a self-aligned local-halometal-oxide-semiconductor device. At first, a semiconductor substratewith a first conductive type having a plurality of shallow trenchisolation formed therein is provided. Then, sequentially forming a gateoxide and a gate electrode between each pair of the shallow trenchisolations over the substrate. Next, forming a first sidewall spaceralong each side of the gate electrode. And then, a second sidewallspacer is formed along one side of each first sidewall spacer.Thereafter, forming a raised source/drain upward on the substratebetween each shallow trench isolation and each second sidewall spacer.Then, each second sidewall spacer is removed. Following, forming alightly doped diffusion region with a second conductive type beingopposite with the first conductive type between each raised source/drainand the gate electrode in the substrate. Finally, forming a halodiffusion region with the first conductive type surrounding the lightlydoped diffusion region. By way of the present method, a local LDD/halodiffusion region with a low junction capacitance is obtained. And then,the operation speed of the MOS device is facilitated.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present invention can be best understood through thefollowing description and accompanying drawings, wherein:

[0013]FIG. 1A to 1C shows schematically cross-sectional views of varioussteps of a conventional method for forming a raised source/drain MOSdevice; and

[0014]FIG. 2A to 2D shows schematically cross-sectional views of varioussteps of the present method according to one embodiment of the presentinvention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Referring to FIG. 2A, a semiconductor substrate 200 with a firstconductive type is firstly provided. The first conductive type is eitherof N type and P type. A plurality of shallow trench isolation 201 isformed in the substrate 200. Then, a gate oxide 202 and a polysilicongate electrode 203 are sequentially formed between each pair of theshallow trench isolation 201 on the substrate 200. Next, forming a pairof first sidewall spacers 204 on opposite sides of the gate electrode203. Then, a pair of second sidewall spacers 205 is formed on oppositesides of the first sidewall spacers 204. The first sidewall spacer 204and second sidewall spacer 205 are formed by way of the following steps:forming a conformal silicon dioxide layer 204 on the polysilicon gateelectrode 203, and then forming a silicon nitride layer 205 on theconformal silicon dioxide layer 204; and anisotropically etching theconformal silicon dioxide layer 204 and the silicon nitride layer 205with reactive ion etch method. The conformal silicon dioxide layer 204can be formed by way of TEOS chemical vapor deposition method. Thesilicon nitride layer 205 can be formed by way of LPCVD method utilizingSiH₂Cl₂ and NH₃ as reaction gases at the temperature of about 700˜800°C. and the operational pressure about 0.1˜1 torr. Alternately, thesilicon nitride layer 205 can be formed by way of PECVD method utilizingSiH₄, NH₃ and N₂ as reaction gases at the temperature of about 250˜400°C. and the operational pressure about 1˜5 torr.

[0016] Subsequently, referring to FIG. 2B, forming a pair of raisedsource/drain 206 upward on the substrate 200 with a thickness about400˜1000 angstroms, each of which formed between each shallow trenchisolation 201 and each second sidewall spacer 205. The raisedsource/drain 206 can be formed of selective epitaxial growth (SEG)semiconductor material, such as silicon and silicon germanium alloy, byway of ultra-high vacuum chemical vapor deposition (UHVCVD) method.

[0017] Referring to FIG. 2C, thereafter, the second sidewall spacers 205of silicon nitride are stripped away by way of wet etching with H₃PO₄aqueous solution.

[0018] Following, referring to FIG. 2D, the gate electrode 203 andraised source/drain 206 are used to act as self-aligned ion implantmasks. When the substrate 200 has P type conductivity, a lightly dopeddiffusion region 207 with N type impurity is firstly formed in thesubstrate 200 between the gate electrode 203 and each of the raisedsource/drain 206. The lightly doped diffusion region 207 can be formedunder the following conditions: arsenic ion is implanted with animplantation energy of 5 to 15 Kev at an implantation dose of 5×10¹³ to5×10¹⁵ ions/cm². Thereafter, a halo implantation is performed to form ahalo diffusion region with P type conductivity 208 surrounding each ofthe lightly doped diffusion regions 207. The halo implantation iscarried out under the following conditions: boron ion is implanted withan implantation energy of 15 to 25 Kev at an implantation dose of 1×10¹³ to 5×10¹⁴ ions/cm². BF₂ ⁺ ion can be substituted for boron ion, withan implantation energy of about 30 Kev to 40 Kev at an implantation doseof of 1×10¹³ to 5×10 ¹⁴ ions/cm².

[0019] Accordingly, a self-aligned local-halo N-channel MOS device withraised source/drain is obtained.

[0020] When the substrate 200 has N type conductivity, the lightly dopeddiffusion region 207 can be formed under the following conditions: boronion is implanted with an implantation energy of 5 to 15 Kev at animplantation dose of 5×10¹³ to 5×10¹⁵ ions/cm². Thereafter, a haloimplantation is performed to form a halo diffusion region with N typeconductivity 208 surrounding each of the lightly doped diffusion regions207. The halo implantation is carried out under the followingconditions: arsenic ion is implanted with an implantation energy of 130to 150 Kev at an implantation dose of 1×10¹³ to 5×10¹⁴ ions/cm².Thereby, a self-aligned local-halo P-channel MOS device with raisedsource/drain is provided.

[0021] In accordance with the present invention, the local-halo regionreduces the junction capacitance to facilitate the operational speed ofthe MOS device. The gate electrode 203 and raised source/drain 206 actas the self-aligned ion implant masks so as to save an extra mask andthe process of the present invention is simplified.

[0022] The preferred embodiments are only used to illustrate the presentinvention, not intended to limit the scope thereof. Many modificationsof the preferred embodiments can be made without departing from thespirit of the present invention.

What is claimed is:
 1. A method for forming a self-aligned local-halometal-oxide-semiconductor device, comprising: providing a semiconductorsubstrate with a first conductive type having a plurality of shallowtrench isolation formed therein; sequentially forming a gate oxide and agate electrode between each pair of said shallow trench isolation oversaid substrate; forming a first sidewall spacer along each side of saidgate electrode; forming a second sidewall spacer along one side of eachsaid first sidewall spacer; forming a raised source/drain upward on saidsubstrate between each said shallow trench isolation and each saidsecond sidewall spacer; removing each said second sidewall spacer;forming a lightly doped diffusion region with a second conductive typebeing opposite with said first conductive type between each said raisedsource/drain and said gate electrode in said substrate; and forming ahalo diffusion region with said first conductive type surrounding saidlightly doped diffusion region.
 2. The method of claim 1, wherein saidfirst conductive type is either of N type and P type.
 3. The method ofclaim 1, wherein said first sidewall spacer comprises conformal silicondioxide.
 4. The method of claim 1, wherein said second sidewall spacercomprises silicon nitride.
 5. The method of claim 1, wherein said raisedsource/drain has a thickness with about 400˜1000 angstroms.
 6. Themethod of claim 1, wherein said raised source/drain comprisessemiconductor material.
 7. The method of claim 6, wherein said raisedsource/drain comprises selective epitaxial growth (SEG) silicon.
 8. Themethod of claim 7, wherein said selective epitaxial growth (SEG) siliconis formed by way of ultra-high vacuum chemical vapor deposition (UHVCVD)method.
 9. The method of claim 6, wherein said raised source/draincomprises selective epitaxial growth (SEG) silicon germanium alloy. 10.The method of claim 9, wherein said selective epitaxial growth (SEG)silicon germanium alloy is formed by way of ultra-high vacuum chemicalvapor deposition method.
 11. The method of claim 1, wherein said secondsidewall spacer is removed by way of wet etching with H₃PO₄ aqueoussolution.
 12. The method of claim 1, wherein said lightly dopeddiffusion region is formed by way of arsenic ion implantation with animplantation energy of 5 to 15 Kev at an implantation dose of about5×10¹³ to 5×10¹⁵ ions/ cm².
 13. The method of claim 12, wherein saidhalo diffusion region is formed by way of boron ion implantation with animplantation energy of 15 to 25 Kev at an implantation dose of about1×10¹³ to 5×10¹⁴ ions/cm².
 14. The method of claim 13, wherein said halodiffusion region is formed by way of BF₂ ⁺ ion implantation with animplantation energy of 30 Kev to 40 Kev at an implantation dose of about1×10¹³ to 5×10¹⁴ ions/ cm².
 15. The method of claim 1, wherein saidlightly doped diffusion region is formed by way of boron ionimplantation with an implantation energy of 5 Kev to 15 Kev at animplantation dose of about 5×10¹³ to 5×10¹⁵ ions/cm².
 16. The method ofclaim 15, wherein said halo diffusion region is formed by way of arsenicion implantation with an implantation energy of 130 Kev to 150 Kev at animplantation dose of about 1×10¹³ to 5×10¹⁴ ions/cm².
 17. A method forforming a self-aligned local-halo metal-oxide-semiconductor device withraised source/drain, comprising: providing a semiconductor substratewith a first conductive type having a plurality of shallow trenchisolation formed therein; sequentially forming a gate oxide and a gateelectrode between each pair of said shallow trench isolation over saidsubstrate; forming a sidewall spacer of silicon dioxide along each sideof said gate electrode; forming a sidewall spacer of silicon nitridealong one side of each said sidewall spacer of silicon dioxide; forminga raised source/drain of selective epitaxial growth semiconductormaterial upward on said substrate between each said shallow trenchisolation and each said sidewall spacer of silicon nitride; removingeach said sidewall spacer of silicon nitride; forming a lightly dopeddiffusion region with a second conductive type being opposite with saidfirst conductive type between each said raised source/drain and saidgate electrode in said substrate; and forming a halo diffusion regionwith said first conductive type surrounding each said lightly dopeddiffusion region.
 18. The method of claim 17, wherein said firstconductive type is either of N type and P type.
 19. The method of claim17, wherein said raised source/drain of selective epitaxial growthsemiconductor material is formed by way of ultra-high vacuum chemicalvapor deposition method (UHVCVD).
 20. The method of claim 19, whereinsaid raised source/drain comprises silicon.
 21. The method of claim 19,wherein said raised source/drain comprises silicon germanium alloy. 22.The method of claim 17, wherein said sidewall spacer of silicon nitrideis removed by way of wet etching with H₃PO₄ aqueous solution.
 23. Themethod of claim 17, wherein said lightly doped diffusion region isformed by way of arsenic ion implantation with an implantation energy of5 Kev to 15 Kev at an implantation dose of about 5×10¹³ to5×10¹⁵ions/cm².
 24. The method of claim 23, wherein said halo diffusionregion is formed by way of boron ion implantation with an implantationenergy of 15 Kev to 25 Kev at an implantation dose of about 1×10¹³ to5×10¹⁴ ions/cm².
 25. The method of claim 23, wherein said halo diffusionregion is formed by way of BF₂ ⁺ ion implantation with an implantationenergy of 30 Kev to 40 Kev at an implantation dose of about 1×10¹³ to5×10¹⁴ ions/cm².
 26. The method of claim 17, wherein said lightly dopeddiffusion region is formed by way of boron ion implantation with animplantation energy of 5 Kev to 15 Kev at an implantation dose of about5×10¹³ to 5×10¹⁵ ions/cm².
 27. The method of claim 26, wherein said halodiffusion region is formed by way of arsenic ion implantation with animplantation energy of 130 Kev to 150 Kev at an implantation dose ofabout 1×10¹³ to 5×10¹⁴ ions/cm².
 28. A self-aligned local-halometal-oxide-semiconductor device with raised source/drain, comprising: asemiconductor substrate with a first conductive type; a plurality ofshallow trench isolation formed in said substrate; a gate electrode witha pair of conformal sidewall spacers formed between each pair of saidshallow trench isolation on said substrate; a pair of raisedsource/drain formed upward on said substrate and between each saidshallow trench isolation and each said sidewall spacer; a pair oflightly doped diffusion region with a second conductive type beingopposite to said first conductive type, each of which formed betweeneach said raised source/drain and said gate electrode in said substrate;and a pair of halo diffusion region with said first conductive type,each of which formed surrounding each said lightly doped diffusionregion.
 29. The device of claim 28, wherein said first conductive typeis either of N type and P type.
 30. The device of claim 28, wherein saidraised source/drain has a thickness about 400˜1000 angstroms.
 31. Thedevice of claim 28, wherein said raised source/drain comprises selectiveepitaxial growth silicon.
 32. The device of claim 28, wherein saidraised source/drain comprises selective epitaxial growth silicongermanium alloy.
 33. The device of claim 28, wherein said lightly dopeddiffusion region has an impurity concentration about 5×10¹³ to 5×10¹⁵ions/cm².
 34. The device of claim 28, wherein said halo diffusion regionhas an impurity concentration about 1×10¹³ to 5×10¹⁴ ions/cm².